yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- SMT2 Backend Treats Non-POT-Sized Memories as next higher POT
- The 'design' command does not clear context as expected
- proc_prune: do not promote partially redundant assignments.
- Adds support for defining the YOSYS_DATDIR location at runtime
- gowin: Fix cells_sim.v to make abc9 work
- make test results in Test: arrays02 -> ERROR!
- iCE40 DSP inference creates technically-unsupported configurations
- Add support for unpacked arrays assignment
- Segfault during 'write_aiger' with simple logic loop `assign x = x & x`
- examples/igloo2 is broken
- Docs
- C++ not yet supported