yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- Segfault during 'write_aiger' with simple logic loop `assign x = x & x`
- examples/igloo2 is broken
- Handle SystemVerilog modport port renaming
- abc git revisions shouldn't be abbreviated
- Error when installation directory contains spaces
- Canot reference items in instantiated module
- proc_arst: Unclear error message when (re)set polarity and sensitivity list do not agree
- ezSAT assertion fail when using freduce
- Removal of conditional code macro definitions for ABC/ABC9
- Suggestions to Improve debug/visualisation in SMT2 backend for SBY
- Docs
- C++ not yet supported