yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- verilog: Bad handling of signedness of real constants in expressions.
- unpacked array in ports
- quicklogic: add PolarPro3 BRAM inference
- verilog: modules can't override global type definitions
- SV return statement and typename function return types
- SV arrays of structs
- specify statement "(A- => B) = 1" causes syntax error if "read_verilog -specify"
- ABC pass mangles synthesized logic on big endian architectures
- anlogic bram and dsp support
- Unexpected case sensitivity in port names
- Docs
- C++ not yet supported