yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- how to support Intel Stratix10
- ice40_dsp, extend_u0 and unextend incorrectly handle sign bits
- when an error happens during `.ys` script execution, yosys should print the script line number that caused the error
- CXXRTL: failed backend invocation leaves empty output file
- No support for Verilog-2001 non-ANSI port aliases
- pyosys interface for Pass doesn't work with virtual functions.
- Allow loading plugins "by name" from more than one source (alt: add a search path for plugins)
- CXXRTL RFE: better debug messages for out-of-bound memory access
- CXXRTL: Strange timings and mismatch in dumped VCD
- Changes to Liberty parser to make it more permissive of paranthetical expressions and keeper cells
- Docs
- C++ not yet supported