yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- extract_fa: Fix `xor3`/`xnor3` inversion bug
- segfault in proc_dlatch when latch is driven by conflicting drivers
- Yosys seems to be inconsistent with the original design.
- Segfault in XAIGER
- Yosys crash: Signal `\A' with invalid width range -1 in cells_map.v"
- Respect $SOURCE_DATE_EPOCH in generate_bram_types_sim.py
- opt_merge: hashing performance and correctness
- 'synth_intel' command,synthesis result is wrong
- Add tri-state support for const eval and add tribuf -propagate option
- Add simulation model for Xilinx BRAM
- Docs
- C++ not yet supported