yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- Assert `flow.wire_comb_defs[it].size() == 1` in `write_cxxrtl`
- Prepend Verilog globals to module AST
- dfflibmap: support flops with enable
- Verilog globals appended to modules instead of prepended
- `sta` command hangs on some designs
- FSM pass equivalence bug
- `tee -q -o <bad-path>` fails silently
- Co-simulation fails for $fa cell
- tests: remove -seq 1 from sat with -tempinduct where possible
- log_deprecated
- Docs
- C++ not yet supported