yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- Reduce default severity of Verific messages that produce warnings on commonly used coding styles
- Latch inferred for x signal
- write_btor: Include `$assert` and `$assume` cells in -ywmap output
- fix ast ternary string extension
- Parameters in other packages
- Yosys Fails to Detect Syntax Violations According to Verilog Standards
- Assertion Failure in genrtlil.cc When Handling Signedness Issue Description:
- Infrastructure to run a Sat solver as a command
- extract: add arbitrary port width matching
- ERROR: Visited AIG node more than once; this could be a combinatorial loop that has not been broken
- Docs
- C++ not yet supported