yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
Triage Issues!
When you volunteer to triage issues, you'll receive an email each day with a link to an open issue that needs help in this project. You'll also receive instructions on how to triage issues.
Triage Docs!
Receive a documented method or class from your favorite GitHub repos in your inbox every day. If you're really pro, receive undocumented methods or classes and supercharge your commit history.
C++ not yet supported3 Subscribers
Add a CodeTriage badge to yosys
Help out
- Issues
- Add autowires in genblk/for expension
- ABC9/AIGER (synth_ecp5) crash "Executing AIGER Frontend" std::vector<_Tp, _Alloc>::.... Assertion '__n < this->size()' failed.
- Please add a flag to generate a simplified graphviz diagram.
- CXXRTL: blackbox output ports cannot generate clock events
- Verilog asynchronous reset pattern leads to corrupted `$check`, `$print` control signals
- smtbmc: Scalability improvements for cexenum
- cxxrtl hangs on a loop
- It seems that a compilation syntax error occurred with yosys
- Registers created by "write_smt2" could be wires by"write_verilog"
- Support for GAL and ATF-series SPLDs
- Docs
- C++ not yet supported