yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
Triage Issues!
When you volunteer to triage issues, you'll receive an email each day with a link to an open issue that needs help in this project. You'll also receive instructions on how to triage issues.
Triage Docs!
Receive a documented method or class from your favorite GitHub repos in your inbox every day. If you're really pro, receive undocumented methods or classes and supercharge your commit history.
C++ not yet supported3 Subscribers
Add a CodeTriage badge to yosys
Help out
- Issues
- verilog: indirect AST_CONCAT and AST_TO_UNSIGNED port connections
- Verific doesn't represent write port priority
- `memory_collect` makes up priority relationships between two `$memwr`
- fmt: Extend string handling for SystemVerilog
- Add an option to synth to enable the booth lower power option
- Add support for unpacked structs
- sim: Add `-assert-cover` option to assert covers were reached
- ABC9 on ice40 causing "ERROR: Visited AIG node more than once; this could be a combinatorial loop that has not been broken"
- Misoptimization of wide shifts
- Error at ICE40_DSP pass: coAssert `nusers(O.extract_end(i)) <= 1' failed in ./passes/pmgen/ice40_dsp_pm.h:388.
- Docs
- C++ not yet supported