yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
Triage Issues!
When you volunteer to triage issues, you'll receive an email each day with a link to an open issue that needs help in this project. You'll also receive instructions on how to triage issues.
Triage Docs!
Receive a documented method or class from your favorite GitHub repos in your inbox every day. If you're really pro, receive undocumented methods or classes and supercharge your commit history.
C++ not yet supported3 Subscribers
Add a CodeTriage badge to yosys
Help out
- Issues
- Assert `arg->is_signed == sig.as_wire()->is_signed' failed
- accept "inout" on interface modports
- Bad assignment in CXXRTL under specific conditions
- Inconsistent handling of multiple default_nettype directives
- `rename -wire` affects quality of results in OpenROAD
- Yosys optimization alters circuit functionality
- Special consideration of x-bits by celledges data
- Tech lib DSP_A/B_MINWIDTH value change causes ABC9 error
- Share pass uses too much system memory for large combinatorial networks
- read_blif: Represent sequential elements with gate cells
- Docs
- C++ not yet supported