yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- iCE40 DSP inference: Inferred multiply-add not working if parentheses omitted
- opt_expr prevents driver/constant conflict warning
- Yosys is missing a FIRRTL frontend
- Speed opt. Compared std 11, 14, 17, 2a.
- Poor error message with two always blocks named the same
- Selecting one of several cell types in dfflibmap based on timing/area tradeoffs
- Source locations for some elements are missing or off by 1
- Add support for variable cell instance name and type via attribute
- Add support for QuickLogic devices
- rmports doesn't remove unused module output.
- Docs
- C++ not yet supported