yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- ABC9 performs worse than ABC for iCE40
- Add generic `add -cell` interface
- Xilinx's RAMB36 inference
- Better document exists-forall problem support
- Broken OBUFT inference in submodules
- valgrind issue for `read_verilog -specify` on blackboxes
- Use a proper interface for Verilog source location information
- Appearance of `ifnone` in specify blocks crashes Verilog frontend
- Recursive module instantations cause stack overflow
- $finish statement in always blocks produce errors
- Docs
- C++ not yet supported