yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- yosys fails in synthesizing flip-flop with asynchronous reset and ternary operator ?:
- "abc -liberty ..." maps to LUTs not the provided library if the "-dress" option is used.
- Yosys generates netlist using too many LUTS
- Synthesis taking a lot of time (memory block?)
- Support set_dont_use
- Techmap to yosys/examples cmos counter using custom 74LVC** IC.
- Regarding removal of buffers and directly using the nets
- memory_libmap creates initialized registers but some architectures don't support them
- Possible cxxrtl simulation bug
- Print backtrace on abort/assert
- Docs
- C++ not yet supported