yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- Expose dfflegalize -mince, -minsrst in synth scripts
- Wider ports in SystemVerilog interfaces are treated as single bit wire
- runtime assert error r=ERROR: Assert `count_id(wire->name) == 0' failed in kernel/rtlil.cc:2022. e=
- yosys 0.23: write_rtlil/read_rtlil for a hierarchical parametric design fails during hierarchy check
- `write_rtlil` and `read_rtlil` won't recreate the same design
- Yosys 0.23+45 (git sha1 a64ed824e, clang 10.0.0-4ubuntu1 -fPIC -Os)
- Selectively flatten by size
- CXXRTL edge detector not working for non-input clocks
- Globally defined SV function breaks CXXRTL export
- write_smt2: Error when using "-nobv" option
- Docs
- C++ not yet supported