yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
Triage Issues!
When you volunteer to triage issues, you'll receive an email each day with a link to an open issue that needs help in this project. You'll also receive instructions on how to triage issues.
Triage Docs!
Receive a documented method or class from your favorite GitHub repos in your inbox every day. If you're really pro, receive undocumented methods or classes and supercharge your commit history.
C++ not yet supported3 Subscribers
Add a CodeTriage badge to yosys
Help out
- Issues
- xilinx: Add support for shift register mapping on LUT4 devices.
- feedback loop missing in logic cell.
- Enable LGTM for code analysis (Semmle)
- Support Xilinx XC9500XL CPLD series
- Instance of empty module remains in results of mxe synthesis
- Optimisations in OPT_LUT pass
- mul2dsp.v doesn't handle variable-width DSP blocks
- ERROR: Assert `current_val[i].wire != NULL || current_val[i] == value.bits[i]\' failed in ./kernel/consteval.h:79.
- ERROR: Assert `lut_slacks[node] >= 0' failed in passes/techmap/flowmap.cc:1295.
- Support for math operations on real constants
- Docs
- C++ not yet supported