yosys
https://github.com/cliffordwolf/yosys
C++
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- Issues
- WIP: Add output register inference for bram
- How to identify bit-level dffsr ?
- opt_clean reverses some connections
- Fix global cache destruction in IdString class
- Initial block with $readmemh ineffective with Lattice ECP5-25F FPGA
- cxxrtl: Verilog frontend's handling of `$meminit` breaks a lot of assumptions
- Add support for unpacked arrays assignment
- Properly specify and reimplement opt_clean/clean
- cleaning enhancements see #2048
- Add support for QuickLogic devices
- Docs
- C++ not yet supported