yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
Triage Issues!
When you volunteer to triage issues, you'll receive an email each day with a link to an open issue that needs help in this project. You'll also receive instructions on how to triage issues.
Triage Docs!
Receive a documented method or class from your favorite GitHub repos in your inbox every day. If you're really pro, receive undocumented methods or classes and supercharge your commit history.
C++ not yet supported3 Subscribers
Add a CodeTriage badge to yosys
Help out
- Issues
- A topological loop is generated after using async2sync
- create a pip install package wheel for Windows
- Abnormal output
- make error 'abc' is not configured as a git submodule.
- read_verilog doesn't respect `signed` keyword
- Yosys seems to handle bit operations on empty strings inconsistently with the original design.
- Wired-or (wor) wires generate $or / $reduce_or cells in output
- No bad property in btor2 file generated from verilog (`write_btor` should error for `$check` cells)
- Add support for SystemVerilog's `==?` and `!=?` operators
- Inout can't be read with constant value
- Docs
- C++ not yet supported