yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- Please add a flag to generate a simplified graphviz diagram.
- CXXRTL: blackbox output ports cannot generate clock events
- Verilog asynchronous reset pattern leads to corrupted `$check`, `$print` control signals
- smtbmc: Scalability improvements for cexenum
- cxxrtl hangs on a loop
- It seems that a compilation syntax error occurred with yosys
- Registers created by "write_smt2" could be wires by"write_verilog"
- Support for GAL and ATF-series SPLDs
- verilog: indirect AST_CONCAT and AST_TO_UNSIGNED port connections
- Verific doesn't represent write port priority
- Docs
- C++ not yet supported