yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- Create duplicate GND_NET in one cell
- Synthesis results can change based on comments or blank lines in Verilog source
- Undef propagation in power operator
- gowin: -nolutram needed for simple initialised memory read/write module, otherwise spurious writes corrupt values on startup
- yosys fails in synthesizing D flip-flop
- Error for partly out-of-bounds part selections
- ice40: BRAM is replaced with DFFs even when conditionally assigned read buffer is exhaustive
- WIP: Add output register inference for bram
- Sort cells topologically
- Equivalence fails when using full adder mapping
- Docs
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