yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- Avoid static initialization order fiasco for global logging objects.
- Feature request: Variables of data type real in initial construct
- ABC9/Aiger: Assert `count_id(cell->name) == 0' failed in kernel/rtlil.cc:2027
- Add parsing of verilog module port aliases (fixes #3334)
- Yosys can't parse port renames in module declaration
- submod command introduces 'inout' ports which results in simulation failures
- Yosys fails to parse two-level-deep function calls in always_comb if the second call reads a field.
- Parsing failed due to real constant problem
- abc9: break conflict between boxes and outputs
- No equivalent circuit is output by `write_verilog`
- Docs
- C++ not yet supported