yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- Lattice ECP5: primitive instantiation sometimes yields 'cells_not_processed'
- Lattice ECP5: Module `FD1P3DX' does not have a port named 'q'.
- Yosys Verilog frontend: module parameters
- Attribute to force a signal to be used "as-is" (like if coming from a blackbox).
- Equivalence checking between verilog netlists
- firrtl: Add support for yosys' $lut cell
- Resource limit support in yosys
- Yosys tcl command substitution does not return the results of the command
- CXXRTL: ERROR: Assert `!is_lhs' failed in backends/cxxrtl/cxxrtl_backend.cc:969
- How to use equiv_add command?
- Docs
- C++ not yet supported