yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- The simplification of for-loop doesn't produce the expected behavior
- readmem[hb] spuriously called with module parameter default value
- synth_ice40 -dsp crashes when SB_MAC16 is manually instantiated
- Feature request: SystemVerilog static casts
- active low enable for tristate buffer
- Verilog backend: pack identical signals in concatenation
- cxxrtl blackbox behavior issue / possible bug ?
- Docker file & github docker hub
- Fixing issues found with sanitizers
- Initial block with $readmemh ineffective with Lattice ECP5-25F FPGA
- Docs
- C++ not yet supported