yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- `extract` pass treats outputs of a sub-circuit as inputs (may be a bug)
- `autoname` memory usage very high with CPU generated from `ghdl-yosys-plugin`.
- cxxrtl: Verilog frontend's handling of `$meminit` breaks a lot of assumptions
- CXXRTL doesn't approach steady state on O4 when routing signal via module
- In CXXRTL edge eval is before calculating value
- hierarchy -chparam cannot decode string parameter value
- Revert "Merge pull request #641 from tklam/master"
- ENABLE_NDEBUG = 1 fail.
- verilog: Bad handling of signedness of real constants in expressions.
- unpacked array in ports
- Docs
- C++ not yet supported