yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- No error thrown for nonblocking procedural assignment to a wire
- SystemVerilog interface fields are implicitly defined?
- Input default value handling is not consistent
- Unsupported argument binding by name
- ABC takes a long time on larger circuit (LUT mapping)
- python: AttrObject member functions not available in derived classes
- CellEdgesDatabase needs fix for shift operations
- Python bindings, OS X
- Circuit takes long time to read (and synth)
- read_liberty doesn't support the name_list syntax
- Docs
- C++ not yet supported