yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
Triage Issues!
When you volunteer to triage issues, you'll receive an email each day with a link to an open issue that needs help in this project. You'll also receive instructions on how to triage issues.
Triage Docs!
Receive a documented method or class from your favorite GitHub repos in your inbox every day. If you're really pro, receive undocumented methods or classes and supercharge your commit history.
C++ not yet supported3 Subscribers
Add a CodeTriage badge to yosys
Help out
- Issues
- Non-ANSI port declarations ignore default_nettype none
- Feature request: For loops with a variable in the end-condition
- Internal module wires are not accessible using dot notation
- Finite state machine equivalence; checking designs with different number of ports
- Please run afl-fuzz against yosys
- What are the system verilog keywords allowed in the assertions inside a Verilog design
- Feature request: Splitting and generating hierarchical designs for larger designs
- EDIF: add support for different flavors of bit indexing
- non-ANSI module declaration with default port values??
- Calculate a min typ max using .lib
- Docs
- C++ not yet supported