yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- Preservation of signedness flag on attribute values inconsistent
- techmap should warn when CONSTMSK/CONSTVAL are used with a nonexistent port
- qlf_k6n10f: leave unused clocks disconnected
- `cxxrtl` output port changes value after back to back `.step()`
- opt_expr: limit effort to reduce runtime on anomalous designs
- read_verilog: array of instances parsing assertion failure
- proc_dff: bit-granularity optimizations and refactoring
- Verilog: Mixing integer and real values causes error
- Docs issues for offline pdf builds
- Refactor full_selection
- Docs
- C++ not yet supported