yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- Properly specify and reimplement opt_clean/clean
- manual: Cannot `make manual`: missing `APPNOTE_010_Verilog_to_BLIF.pdf`
- clean: remove unused wires even with (* init *) on
- Produced edif gives Multiple Driver Nets error.
- cleaning enhancements see #2048
- yosys-abc failed return code 127; libreadline6 vs libreadline7
- pyosys API: Silent aborts (segfault/assert())
- pyosys autogeneration: Parser skips a few functions due to line breaks in header
- iCE40 DSP inference: Inferred multiply-add not working if parentheses omitted
- opt_expr prevents driver/constant conflict warning
- Docs
- C++ not yet supported