yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- Error Arises During Synthesis due to Verilog Code Structure
- Async reset inference ignores process switch polarity
- Yosys Verilog Parsing Error: Issue in AST Generation
- Assertion Failure in AST Processing during Verilog Synthesis
- write_cxxrtl: missing parameter when instantiating a Verilog blackbox module.
- tribuf -formal with a single driver of the tristate net connects input to output
- subsicuit $_DFFE_NP_ Issue
- sim: Evaluate all cells once
- [abc] Assertion src/base/abc/abcAig.c:1134: void abc::Abc_AigUpdateLevelR_int(abc::Abc_Aig_t *): Assertion `Abc_ObjIsNode(pNode)' failed.
- Split off evaluable/combinational flags in `celltypes.h`
- Docs
- C++ not yet supported