yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
Triage Issues!
When you volunteer to triage issues, you'll receive an email each day with a link to an open issue that needs help in this project. You'll also receive instructions on how to triage issues.
Triage Docs!
Receive a documented method or class from your favorite GitHub repos in your inbox every day. If you're really pro, receive undocumented methods or classes and supercharge your commit history.
C++ not yet supported3 Subscribers
Add a CodeTriage badge to yosys
Help out
- Issues
- Improved `sim` handling of `$display`/`$print`
- check: Un-sigmap the `check` command
- Write first RAM using blocking assignments synthesized as Read first RAM
- `DP16KD` blackbox model is missing at least `CLKAMUX` and `CLKBMUX` ports.
- <<EOT doesn't work from the command line
- Multibit `reg` crashes Yosys without an error
- Failed to parse Verilog code with escaped identifiers
- "write_json" sometimes preserves the leading "\" of an escaped identifier, sometimes not.
- "Failed to resolve identifier XXX for width detection" with System Verilog interface element
- no FSM in design, execute "synth" without "-nofsm", some logic is recognized as FSM and the number of register will become more
- Docs
- C++ not yet supported