yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- ice40: Implement simple SB_HFOSC and SB_LFOSC for simulation
- nlatch Verliog code synthesis question
- Liberty front end doesn't properly parse boolean expressions
- Improve write_verilog speed
- How to figure out the actual name of the flipflop in yosys?
- SV Type parameters are not supported
- Improve detection of multiply declared signals in SV frontend
- Yosys fails to parse "endmodule;" due to a semicolon
- feat(parser): RFC for concurrent assertions
- abc commit 0d0063f7 breaks tests/arch/ice40/rom.ys (and tweaks to yosys-abc release process)
- Docs
- C++ not yet supported